`timescale 1ns / 1ps


module divider(
    input clk,
    input resetn,
    output signed [6:0] minus_1
    );
    reg c11,c21,c2_1,c3,c3_1,c3_2;
    wire [18:0] counter1,counter2,counter3;
    reg [17:0] counter1_reg,counter2_reg,counter3_reg;
    
parameter real frac =49999;
    always@(posedge clk or negedge resetn) begin
        if(!resetn) begin
            counter1_reg<=18'b0;
            counter2_reg<=18'b0;
            counter3_reg<=18'b0;
            c2_1    <=1'b0;
            c3_1    <=1'b0;
            c3_2    <=1'b0;
        end
        else begin 
        
        counter1_reg<=counter1[17:0];
        
        counter2_reg<=counter2[17:0];
        c2_1      <=counter2[18];    
            
        counter3_reg<=counter3[17:0];
        c3_1    <=counter3[18];
        c3_2    <=c3_1;
        end
        
    end 
assign counter1=counter1_reg+frac;
assign counter2=counter2_reg+counter1_reg;
assign counter3=counter3_reg+counter2_reg;

assign  minus_1=counter1[18]+counter2[18]+counter3[18]+c3_2-c2_1-c3_1-c3_1;
//assign  minus_1=counter1[18]+counter2[18]-c2_1;
    //assign  minus_1=counter1[18];
endmodule
